Design And FPGA Implementation Of Digital Filter Based On RNS

The finite impulse response（FIR）filter is a basic component of digital signal processing（DSP）,and it has the advantages of being easy to implement,stabilized,and linearly phased.With the rapid development of modern communication technology,FIR filters are widely used in many DSP fields such as voice and image processing,noise reduction,and pulse formation.However,the FIR filter in traditional two's complement system（TCS）has been difficult to achieve both the real-time and high-precision requirements in the context of ultra-high-speed information flow.Delay is a very important factor that affects the performance of FIR filter.The FIR filter performs intensive multiplication and accumulation,and the performance of the binary adder and multiplier is affected by the propagation delay of the carry chain.Therefore,reducing the propagation delay of the carry chain and improving the efficiency of the arithmetic unit have been the direction of people's research.As an unprivileged system,the residue number system（RNS）has the characteristics of natural parallelism and strong fault tolerance.It has become a new choice for the design of high-performance filter.In this thesis,a high-order FIR filter and a biorthogonal wavelet filter banks based on RNS with the five moduli set{2ⁿ-1,2ⁿ,2ⁿ（10）1,2^n-1-1,2^n（10）1-1}are designed.In order to improve the performance of the filter,the modulo adder based on the parallel prefix structure is optimized in this paper,and a modulo 2ⁿ-1 adder based on the three-prefix operator is given.This structure can calculate three pairs of generate and propagate signals at the same time.Compared with the normal modulo 2ⁿ-1 adder,one prefix level of the adder is reduced.In addition,this modulo 2ⁿ-1 adder not only obtains a better speed,but also has a representation of“000...00”for its calculation result.The binary-to-residue conversion of the input is realized by the pure combinational logic circuit based on the carry save adder（CSA）tree.Compared with the general filter structure,the accumulative operation is combined into the addition of the partial product of the multiplier in the proposed FIR filter.Thus the delay is further reduced by using a full adder instead of the use of a modulo adder.In addition,by calculating the residue of the intermediate result of the CSA,the increase in bit width caused by the addition is avoided,thereby the complexity of the whole operation is reduced.This thesis implements a high-order RNS FIR low-pass filter based on FPGA.The input of the filter is converted from a binary to a RNS representation through the forward converter,and the operations are independently performed in multiple parallel channels.Finally,the backward converter transforms the output from RNS format to binary representation.After software simulation and hardware testing,the RNS FIR filter removes high-frequency signals and preserves low-frequency signals.The synthesized results show that the maximum operating frequency of the filter is 341.30MHz and the power consumption is 2469 mw.By comparing the figure of merit values,the RNS FIR filter implemented in this thesis has a better performance.In addition,an RNS biorthogonal wavelet filter bank is implemented based on FPGA.The filter bank consists of two high-pass filters and two low-pass filters.Through software simulation and hardware testing,the noise signals could be filtered correctly by the filter bank.The synthesized results show that the maximum operating frequency of the RNS filter bank is 391.42 MHz,and the power consumption is 805 mw.By comparing the figure of merit with other designs,the RNS biorthogonal wavelet filter bank realized in this thesis behaves a better performance.