The Design Of The Modulo Adder And Multiplier Unit In RNS

With the time going and the evolution of the technology, Moore’s law will gradually come to an end. And faced with the explosion of information and data, the way that improves the state of the art to improve performance of very large scale intergrated circuit can not satisfy demand in the industrialized information society.So the method which the improvements in the algorithms increase performance of high-speed signal processing has been more and more given much importance. And residue number system meets the requirements. Residue number system that has the natural features of non-weight and parallel have been widely used in high speed digital process system. Residue number system is that make complex data separate into inde-pendent data in parallel process. This processing can dramatically reduce the bit width of the data, cut the length of carry and reduce the critical path delay. Comparing with conventional binary system, residue number system has a shorter critical path, less area and power consumption. The performance of adder unit and multiplier unit which is the basis of high-speed digital signal processing has been gotten more and more attention. So the article will place emphasis on design of adder unit and multiplier unit in the residue number system.To improve the capacity of residue number system and enlarge the dynamic range of channel. The article proposes two modulo 2n+2p ± 1 adder units and two modulo 2n - 2P+1 multipliers unit on two different condition. The article design as follows:1.The article proposes two modulo 2n+2P ± 1 adder units, which will select the carry of the adder to modify in order to gain final correct sum results. In this design, the theory of the reuse in overlapped unit improve the circuit performance. The modulo 2n+2p+1 adder circuit performance has been improved 8.8% and 9.4% compared with data in the the literature. The modulo 2n+2p - 1 adder circuit performance has been improved 28.3% and 25.6% compared with data in the the literature.2.The article proposes two modulo 2n - 2p+1 multiplier units. The one is suitable for properties equilibrium. It splits the product and use CSA unit to decrease the number of part product. At the end, it use a modulo adder unit to get the final result. Compared with the literature, the average delay of the propose circuit is reduced by 7.5%, and the average area is reduced by 1.4%. The other one use Booth encoder to decrease the number of part product and splits the part product. At finial, the high-speed modulo multiplier unit use CSA units and modulo adder to get the modulo product result. Compared with the literature, the average delay is reduced by 11.9%, which is suitable for high speed.Because of unit gate model static analysis with defectiveness, the article will give a real circuit synthesys report to compare. The article uses Verilog HDL language to build the model for the proposed circuit, and uses Design Compiler with TSMC 90nm library to do the synthesys. Finially, compared with circuit synthesys report, the proposed circuit has better performance.