| CMOS circuits are being investigated for use at ever increasing frequencies as researchers find ways to get around the high loss and low electron mobility associated with silicon substrates. High speed CMOS devices with fT greater than 150 GHz have been presented, and design strategies for silicon interconnects out to 50 GHz have been established. However, there are few examples of working circuits fabricated in standard CMOS processes at frequencies higher than 10 GHz.; This thesis reviews current practices for the design of high speed CMOS MOSFETs and low loss transmission line, and then presents a study of three high frequency CMOS devices. Firstly, the design of narrowband amplifiers is examined with particular attention paid to the use of parallel feedback for gain enhancement. Measured results for two amplifiers are presented including, a 20 GHz amplifier with a maximum gain of 8.8 dB at 20 GHz and a 23 GHz amplifier with a maximum gain of 5.7 dB.; Secondly, the design of broadband traveling wave amplifiers (TWAs) is presented. Transmission line design is examined, and a novel gain cell is presented that has superior properties for TWAs than do standard CMOS MOSFETs. Two TWAs are presented, one of which includes an internal drain bias network (the first such device known). The TWA with an internal drain bias network achieved a gain of 5 dB out to 10 GHz while drawing a total of 110 mA. Another TWA without an on-chip bias network achieved a gain of 8 dB out to 10 GHz while drawing a total of 124 mA. These are the highest frequency CMOS traveling wave amplifiers known.; Finally, the design of dielectric resonator oscillators is examined. Coupling between a dielectric resonator (DR) and a transmission line over a silicon substrate is examined, and the design of a negative resistance element using a MOSFET with series and parallel feedback is studied. Simulation shows that the negative resistance device at 26 GHz can be designed with a CMOS process, but the close proximity of the ground plane prevents a transmission line from coupling to a dielectric resonator. However simulations show that a DRO should be possible by placing the DR on an insulating substrate, such as alumina, and wirebonding it to the negative resistance device on the CMOS chip. Harmonic balance analysis and an FEM 3-dimensional electromagnetic solver were used to design a 22 GHz DRO. In simulation it had an output of 4 dBm at 22.17 GHz with a phase noise of −87 dBc at 10 kHz offset.; The study of these three circuits shows that CMOS circuits operating at 10 to 20 GHz are becoming viable for certain applications. Due to the low cost of using these processes and the large number of personnel and facilities dedicated to silicon design it is expected that CMOS technologies will continue to make significant inroads into the field of microwave circuits. |
