| A compact, low loss, optical tap technology is critical for the incorporation of optical interconnects into mainstream CMOS processes. An asymmetric, vertical multimode interference effect based device is investigated that has the potential for very high speed and optically efficient performance in a compact geometry and in a CMOS compatible process. 2-D and 3-D device simulations have confirmed a low excess optical loss on order of 0.2 dB, and a nominal 40% (2.2 dB) optical coupling into the CMOS circuitry over a wide range of guide to substrate distances. Simulated devices are on the order of 25 to 30 μm in length and as narrow as 1 μm for channel guide based designs. High temperature, hybrid polymer materials used for commercial CMOS inter-metal dielectric layers were targeted for optical waveguide and tap fabrication and were incorporated into the models. Tap structures, based on 5 μm wide ridge waveguides with 1 μm thick cores, were fabricated on silicon substrates at guide to substrate spacings up to 6 μm. Devices were optically tested for polarization sensitivity and insertion losses, with the experimental results showing good agreement with theory. Low excess losses on order of 0.3 dB were confirmed, as was the effectiveness of a thick isolating spacer layers. Low cost, silicon CMOS based processing makes the new tap technology especially suitable for computer multi-chip module and board level interconnects, as well as for metro fiber to the home (FTTH) and fiber to the desk telecommunications applications. |
