Yield Enhancement through Pre- and Post-Silicon Adaptation

Achieving a consistently high yield is always a key design objective. However, circuits designed in aggressively scaled technologies face more stringent design constraints and increased process variability. Traditional guard-band design methodologies that assume worst-case environmental factors and minimum feature size may reach overly conservative decisions and inevitably deteriorate the yield. Hence, design for yield (DFY) in nano-meter regime has become highly imperative for chip designers.;This thesis focuses on several topics in yield enhancement and attempts to answer two basic questions (1) how to achieve a high yield and (2) how to achieve a consistently high yield. The first question is associated with several yield optimization issues. One key issue that complicates parametric yield optimization is the negative correlation among design constraints. In the first part of the thesis, we discuss the power-performance correlation and present a novel yield optimization framework by selecting body bias at design time. The framework considers both inter- and infra-die variation and then explores the possible body bias selection for gates by using a feature extraction technique. The gates with similar features are then grouped together and fed to the optimization framework to maximize the joint power-performance yield. The second and third parts of the thesis discuss the impact of oxide breakdown reliability on yield. For recent technology nodes, chip reliability has become a pressing concern in DFY. This thesis places the focus on oxide breakdown reliability, which is one of the key factors that set constraints on the operating supply voltage of the chip. Any pessimism in oxide breakdown reliability analysis may eventually degrade the yield. We therefore propose a process and temperature variation-aware method for full chip oxide breakdown reliability analysis. Based on that, we further develop a reliability and performance management scheme by analyzing limited post-fabrication measurements. This post-silicon method helps designers tightly bound the chip reliability and hence enables the use of available margin to boost the system performance while meeting the design lifetime. Since pre- and post-silicon optimization usually targets at the same design objective, it is therefore necessary to perform certain coordination to avoid repeated optimization. In the fourth part of the thesis, we explore the interaction between gate sizing (pre-silicon) and adaptive body biasing (post-silicon) to improve the yield optimization efficiency while maintaining the tunability for a particular target.;It has been observed that even for the same design with exactly the same design optimization, the yield may happen to be inconsistent from lot to lot. A major reason behind this inconsistency is the inability to capture the process variation change during the fabrication. In the last part of the thesis, we address the second question to achieve a consistently high yield by using a dynamic variation extraction model. Unlike the traditional design-time variation model that is static and constructed by measuring hundreds of testing wafers, the proposed post-silicon model is extracted from the measurements of product wafers. The model then dynamically adapts itself to the process change by reusing information from past wafers to validate and improve the model. Such a model is more accurate (or less pessimistic) than a design-time model and also helps reduce the yield inconsistency.