Yield-reliability modeling for integrated circuits: Theory and experimental verification

This dissertation presents a unified approach to yield and reliability modeling for integrated circuits. The model is based on the experimental fact that the same defects that cause initial wafer test failures also cause early-life reliability failures. Defect-based yield models, traditionally only applied to project initial wafer test yields, can therefore be extended to incorporate early-life reliability prediction.; Modern defect-based yield models for integrated circuits must account for the fact that defects over semiconductor wafers tend to cluster or group together. The negative binomial distribution, long known to accurately describe initial wafer test yields, is used to describe this behavior. It will be shown that this defect distribution can accurately predict not only the number of wafer test failures, but also the number of early-life reliability failures.; The yield-reliability model is first used to estimate the early-life reliability of repairable memory die. Repairability allows many of the defects discovered at initial wafer test to be bypassed so that the die is once again functional. It will be shown, however, that memory die that have been repaired are significantly less reliable than die with no repairs. This is quantified with the yield-reliability model and shown to be in excellent agreement with experimental data obtained from IBM Microelectronics.; The clustering of defects is not limited to a single die. In fact, defect clusters can be large enough to affect multiple die or even entire wafers. Since die from relatively low yielding regions are near a relatively large number of defects, die emerging from these regions should be more likely to contain subtle, early-life reliability defects, than die from relatively high yielding regions. That this is true is demonstrated with data provided by IBM Microelectronics. Again, the yield-reliability is shown to accurately predict early-life reliability, in this case for die from wafer regions with various values of local yield.; In addition to estimating the number of early-life reliability failures, the yield-reliability model also allows one to determine the time at which these failures occur. This information can then be used to optimize expensive stress tests such as burn-in, which attempt to precipitate early-life reliability failures before they are shipped to the customer. Using the integrated yield-reliability model it is shown that integrated circuits that are segregated by number of repairs or by local region yield can exhibit very different failure rates during a stress test such as burn-in. These populations therefore require different burn-in durations to reach the same level of reliability.