Tomography as a metrology technique for semiconductor manufacturing

This dissertation is concerned with exploring the feasibility of a class of sensors which provide temporally and spatially resolved wafer state information during semiconductor manufacturing. The common theme shared by this class of sensors is that they are based on Electrical Impedance Tomography (EIT). EIT is a non-destructive in vivo imaging technique principally used in medical applications.; The basic idea of Electrical Impedance Tomography is to image the conductivity distribution in the interior of a conductive object by performing simple electrical measurements on the periphery of the object. In a semiconductor manufacturing context, physical and chemical effects during semiconductor manufacturing can induce a change in conductivity in the interior of a wafer. EIT techniques can be used to infer these conductivity changes. In turn, these changes can be related to the physical and chemical effects using appropriate models.; In this thesis, we first discuss the status quo of metrology methods in use in the semiconductor manufacturing industry. This discussion is followed by a thorough introduction to Electrical Impedance Tomography. We then argue that Electrical Impedance Tomography can be a compelling technique to obtain spatially and time-resolved wafer state information during wafer processing. To illustrate these ideas, we design and analyze two EIT based sensors for use during semiconductor manufacturing.; Our first sensor is a device to measure etch rates or film thicknesses. We have designed, fabricated and tested this sensor. We use standard EIT techniques to estimate the conductivity distribution of a thin film of conductive polysilicon across a wafer. The estimated conductivity distribution can, in turn, be related to the thickness of the polysilicon film from first principles. Differential thickness measurements from our prototype etch rate sensor correlate very well with optical thickness measurements.; Next, we propose a novel EIT based sensor which can provide temporal and spatial wafer surface potential information during plasma processing. Our design relies on a resistive network containing discrete transduction elements whose conductivity is modulated by the variable of interest. To assess our idea, we performed simulation studies on a prototype sensor which uses depletion mode NMOSFETs as transduction elements. We have obtained promising simulation results with this novel EIT based metrology technique.