Scanning probe metrology of semiconductor line edge roughness

Over the years, the size of components that make up microelectronics integrated circuits (IC) has steadily decreased. A key measure of the size of features used to fabricate IC components is the width of patterned lines. The relative uncertainty associated with determining the width of these lines has increased, as the width itself decreases. A major source of this uncertainty is the deviation of the line edge from a straight line, otherwise known as line edge roughness (LER). LER has been linked to current leakage in devices, and is becoming an important contributor to the lithography error budget. The tools currently used to measure LER have limitations and may not be able to meet the LER measurement needs of the semiconductor industry. This is because semiconductor lines are complex three-dimensional structures with vertical surfaces and the available instruments are not optimized for such measurement. Hence, there is a need for robust LER metrology techniques. We explore the use of the atomic force microscope (AFM) for measuring LER. There are several implementations of the AFM, and it is not clear if all of them measure LER in the same way. The goal of this study is to explore how different implementations of the AFM measure LER, and what improvements are needed to achieve increased resolution. Results of measurement comparisons using different AFMs are presented, and requirements for AFM based LER metrology are outlined.