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Research On Scheduling Of Batch Processor In Furance Area Of Semiconductor Wafer Manufacturing System

Posted on:2012-01-10Degree:MasterType:Thesis
Country:ChinaCandidate:C LiFull Text:PDF
GTID:2218330362959075Subject:Management Science and Engineering
Abstract/Summary:PDF Full Text Request
As one of the most complex manufacturing system today, a semiconductor wafer manufacturing system (SWFS) is characterized by re-entrant process flows, complex production processes and unpredictable equipment downtime, which make the schedule of a SWFS very difficult.The scheduling of batch processor (SBP) in the furnace area has the common features of SWFS. Batch processing facilities are generally bottlenecks in manufacturing systems for a variety of reasons: They are often expensive to purchase so that the utilization of such equipment is usually very high. Furthermore, parts (jobs) usually require long and non-preemptive processing times, so that the facility is unavailable for other parts (jobs) for relatively long period. Thus, rendering an effective scheduling approach of batch processors of SWFS is an important management concern. The major contributions to SBP of this paper are as follows:1) The bottleneck of the SWFS is found in the process of observation on the real semiconductor plant, and through the analysis on process and equipment of the bottleneck, the main scheduling conflicts are found which suggests the idea and direction of the entire research.2) A mathematical model is built for this problem, and through the analysis of the scheduling problem, the complex problem can be broken down to several sub-problem, and the goals of scheduling is established. To solve the scheduling problem of batch processing machine in the furnace district of SWFS, this paper proposes a scheduling algorithm which satisfies the process constraint and equipment limitations. Considering the dynamic arrival of lots and the SWFS's features of large scale and multiple re-entrant processes, the algorism may realize the real-time combinatory dispatching of multi-product and multi-machine by optimizing average waiting time of lots.3) The simulation based experiments are made on a virtual SWFS fab simulation platform (ReS2), which has been modified to match the real production process, and the result shows that the algorithm can significantly improve the fill rate and the utilization of the bottleneck machine and thus shorten the cycle time in real-time dispatching.
Keywords/Search Tags:semiconductor wafer fabrication system, batch processing, bottleneck, scheduling
PDF Full Text Request
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