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Analytical models of batch processing for optimal design of semiconductor manufacturing

Posted on:2001-01-02Degree:Ph.DType:Dissertation
University:Arizona State UniversityCandidate:Phojanamongkolkij, NipaFull Text:PDF
GTID:1468390014957222Subject:Engineering
Abstract/Summary:
Nowadays electronics devices are involved in everyone's daily life. These electronics devices are manufactured in semiconductor wafer fabrication facilities, or wafer fabs. Wafer fabs use hundreds of sequences of chemical processes to build the circuitry on the surface of wafers. Wafer fabs are unique and complex factories; the process flows are far more complex than those of the classical job shop factory. Process operations of the wafer fab can be divided into two main categories, serial-processing and batch-processing operations. Serial-processing operations process one wafer or one lot (collection of wafers) at a time, while batch-processing operations process multiple lots simultaneously.; Even with the complexity, most wafer fabs use simple performance evaluation tools, e.g. spreadsheet models, to perform long-term production planning. These models give rough approximations to key performance measures. More sophisticated production planning technique includes discrete event simulation (DES) models because the DES models provide modeling flexibility to include different levels of detail. Unfortunately, DES is time-consuming and its analysis requires extensive computer resources and statistical knowledge.; Another potentially effective performance evaluation tool that can be used in production planning is queueing network analysis (QNA). QNA is fast and its approximated results do not require statistical interpretation. However, the existing queueing analysis does not adequately estimate the impact of the batch-processing steps.; In this research, a QNA based approach that approximates batching effects on system performance measures, called QNA[B] is studied. QNA [B] provides reasonable estimates of overall system performance measures compared to the DES model, while it is thousands of times faster. In this research, QNA[B] is used to evaluate system performance of a real-world semiconductor manufacturing facility, LSI Logic, for long-term production planning purposes. The QNA[B] model is also applied to determine optimal batching policies at the batch-processing operations for two specific situations. The first situation is to determine batch sizes that minimize the total expected cycle times of lots at the batch-processing operations. The second situation is to determine batch-processing policies that minimize the summation of the weighted expected cycle times of all lot types, where the weights are the importance levels of lot types.
Keywords/Search Tags:DES, Semiconductor, Models, Wafer, QNA, Process, Production planning
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