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Parasitic-aware design and optimization of CMOS RF power amplifier

Posted on:2004-01-23Degree:Ph.DType:Thesis
University:University of WashingtonCandidate:Choi, KiyongFull Text:PDF
GTID:2468390011458154Subject:Engineering
Abstract/Summary:
Almost everyone now owns at least one wireless product, such as a cellular phone, beeper, two-way radio, wireless modem, etc. Due to this exploding popularity, many researchers around the world striving to reduce cost, decrease size, minimize power consumption and increase performance of these wireless products. To satisfy these requirements, a CMOS fully integrated system-on-chip implementation including the RF circuits is one of the most attractive solutions. However, circuit designers face difficult challenges to develop CMOS integrated RF solutions because CMOS speed/power performance is inferior to other technologies such as BJT and GaAs, and the lossy silicon substrates cause poor performance in the passive elements.; A fully integrated RF power amplifier represents one of the most difficult unsolved challenges of CMOS technology owing to the low breakdown voltage of conventional CMOS devices and the adverse parasitic effects associated with the passive elements. To solve these challenges, parasitic-aware design and optimization paradigm is advanced and new circuit design techniques are proposed. The new parasitic-aware design and optimization technique is based on adaptive simulated annealing with tunneling and post optimization PVT sensitivity analysis. The new circuit techniques include a self-bias power amplifier technique and a digitally tuned conduction angle approach for a differential non-linear RF power amplifier employing low breakdown voltage transistors.; The adaptive simulated annealing with tunneling process reduced required the optimization time by 4X compared to conventional simulated annealing. The post optimization PVT method is used to get the most robust and manufacturable design with minimum optimization time. The simulation and test results show that the parasitic-aware synthesis technique minimizes the parasitic effects and maximizes performance; the new circuit architectures reduce the voltage stresses on the CMOS devices, and subsequently improve PA performance compared to previous approaches.
Keywords/Search Tags:CMOS, RF power, Parasitic-aware design and optimization, Power amplifier, New circuit, Performance
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