Design Of 60 GHz CMOS Power Amplifier

The rapid growth of mobile data and the popularity of smart phones have brought unprecedented challenges to wireless service providers overcoming global bandwidth shortages.Millimeter wave technology is widely regarded as the key technologies continue to meet consumer demand for wireless data capacity increases.The license-free60 GHz band has more spectrum than the 2.4 GHz and 5 GHz bands used by existing Wi-Fi products,providing great potential for establishing high-rate short-range wireless communication links.Although the bandwidth is large,the design of power amplifier?PA?is a major challenge in the development of 60 GHz wireless transceivers due to signal attenuation due to oxygen absorption in the 60 GHz band,especially if CMOS technology is chosen to achieve fully integrated 60 GHz wireless system.Although CMOS has higher integration and lower manufacturing cost than high-speed composite semiconductor technology,the operation of low power supply and breakdown voltage and MOSFET proximity frequency makes the design of the power amplifier very challenging.Therefore,designing a PA that meets the requirements of a millimeter wave system is of great significance.In this context,this thesis mainly completes the research and design of CMOS PA in 60 GHz band.For the challenges of millimeter-wave circuit design under the CMOS process,more in-depth research was conducted and the method of millimeter-wave circuit design was discussed.In order to realize a power amplifier applicable to a 60 GHz WPAN,a single-ended and differential power amplifier was designed based on the SMIC 90nm RF_CMOS process.For single-ended power amplifiers that can operate at 60 GHz,they are implemented using a three-stage cascade structure that operates in Class A.The input stage is implemented using cascode structure with adaptive bias to improve gain and reverse isolation.The last two stages are implemented in CS structure to meet the output power and linearity requirements.The use of HFSS modeling to obtain small inductor values for on-chip spiral inductors is used in matching designs,and high efficiency is achieved by simplifying the matching network to reduce circuit losses.Simulation results show under the 1.2V,the power gain at 60 GHz is 16.2dB,the output power at 1dB compression point is 8.2dBm,the saturation output power is 11.4dBm,the peak power added efficiency is 15.3%,and the DC power consumption is 70mW.For the 60 GHz differential power amplifier,a class-A CS pseudo-differential structure that can obtain a large output power is used for design implementation.In order to eliminate the negative influence of the gate-source parasitic capacitance C_GD of the CS structure on the circuit,a cross-coupling capacitor neutralization is used.The technology is used to offset the poor reverse isolation,stability,and low gain caused by the parasitic capacitance C_GD,thereby improving the circuit performance.The simulation results show that under the voltage of 1.2V,the differential power amplifier achieves 17.0dB power gain at 60 GHz,the reverse isolation is better than-50dB,the output 1dB compression point power is 10.2dBm,and the saturated output power is 14.4dBm.The peak PAE is9.1%and the power consumption is 103mW.Post simulation show the power gain is 9.56dB,Psat is 10.0 dBm,and the peak PAE is 6.0%.