| In order to take full advantage of the migration from bulk-Si to SOI technology, existing circuit design guidelines and design verification tools must be revisited. This thesis will cover the following three topics as part of this endeavor.; Circuit design styles. Our effort here focuses on the identification and development of static and dynamic design guidelines that are optimally suited for SOI-CMOS; delay and data integrity are our metrics. First, we investigate the possibility of increased fan-in in SOI gates; complex gates imply reduced switching power. Then, we assess existing design fixes for eliminating bipolar leakage in SOI domino gates. Many of these fixes are shown to aggravate charge sharing. Finally, we present the PHI predischarge method for handling the orthogonal problems of bipolar leakage and charge sharing induced node upset.; Bipolar leakage modeling for switch-level simulators or approximate simulators. Accurately modeling the bipolar leakage requires including the body as an additional node in a complex network of capacitors and diodes; this burdens approximate simulators and conflicts with their speed objective. We present a bipolar leakage model for approximate simulators that avoids such complexity. Unlike previous attempts, our model comprehends the effect of the floating body and is therefore complete.; Cell-based noise analysis tools. In advanced SOI technologies, the input noise may propagate, with little attenuation, through several or many gates. Therefore, accurately modeling noise propagation (from a cell's inputs to its outputs) is of significant importance for cell-based noise analysis tools. We propose and implement two new macromodeling techniques for purposes of building a noise-rule library. Our models capture the cell's output response due to noise at its input. Thus, one may accurately predict the propagated noise, perform failure/sensitivity (stability) analysis, or even hierarchically build the noise abstracts by invoking those high-level macromodels. |
