BJT Device Modeling And IP Circuit Design

The rapid development of integrated circuit raises requirement of integrated circuit manufacturing process, device model is the cornerstone of IC design, and also is the bridge to link IC design and IC manufacturing. Accurate device models for the proper characterization of the actual performance of the circuit are of great importance. Research in the PNP device modeling under bipolar and BiCMOS process has been widely studied in both domestic and overseas , while for the CMOS process the PNP device modeling rarely involves. With the evolution of SOC technology, the requirement to high-performance, high-speed digital and analog IP core is also increased. To conform to IC development tendency, this paper will focus on BJT device modeling under CMOS and BiCMOS process and analog IP core design under CMOS process. Its contents are summarized as follows:(1)Model parameters extraction and modeling on BJT device are carried out under CMOS and BiCMOS processes. Based on the research of BJT device's working mechanism and BJT device structures under several different processes, VBIC model is selected and applied to extract model parameters of tape-out devices. After deep research on extraction method of PNP devices'large signal model parameters under CMOS and BiCMOS processes, according to the different characteristics of the model parameters, the extraction process is divided into the following five parts: resistance parameters extraction, Early effect parameters extraction, current parameters extraction, capacitance parameters extraction and temperature parameters extraction. And different extraction methods are designed to the five parts respectively. After optimizes the extracted parameters for several times to a better fitting effect, these model parameters can better characterize the DC characteristic of the device. At last we do the error analysis on the VBIC model under the BiCMOS process, the results show that the built model error is all within 2%, mostly under 1%, and the RMS is 5.519% which can properly present the dc characteristics. Then we compare the parameters between the VBIC model under CMOS process and Gummel Poon model provided by the foundry, the results show that the error is between 3% ~ 4% under the chartered 0.35μm process, while the error of the self-bulit VBIC model is mostly within 3%, some point error is even less than 1%. So the error precision of the VBIC model is better than Gummel Poon model under chartered 0.35μm process, and can better present the dc characteristics of the model.(2) Two analog IP cores are designed under chartered 0.35μm CMOS process. One is a high-gain fully differential op amp which uses gain-boosting technique and has a CMFB (Common Mode Feed Back) circuit. The other is also a fully differential op amp with CMFB circuit, but its main amplifier is a telescopic structure. In addition, this paper puts forward a novel method for testing the low-frequency gain of fully differential op. Test results show that the telescopic op amp's low-frequency gain is 79.8dB, unity-gain bandwidth is 180MHz. The high-gain op amp's low-frequency gain is 106.8 dB. And telescopic op amp's successfully designed and implemented can significantly prove that the new test method can accurately test the gain of fully differential amplifiers; due to process deviation, mismatching and other reasons, there is a slight gap between the high-gain amplifier's simulation result and test result.The established VBIC model in this paper can be applied to actual circuit design, and the operational amplifier IP core designed in this paper can also be used in ADC, DAC, bandgap reference, power management IC and other complex IC circuits.