| A new delay insensitive asynchronous logic methodology is presented. It is characterized by gate level pipelining to achieve high throughput. An auto-sleep mode together with supply voltage control logic reduces leakage power consumption. The new approach uses only conventional synchronous computer-aided design (CAD) tools and standard cell libraries. Several benchmark circuits are tested to prove this new asynchronous logic has high performance and is very robust even when operating in the sub-threshold regime. |
