Research On Optimization Of Software Pipelining For IA-64 Architecture

Software pipelining (SWP) is an effective technique for loop optimization. It reduces the loop execution time by overlapping the execution of successive iterations. IA-64 is one kind of Explicitly Parallel Instruction Computing (EPIC) architectures. It provides a powerful set of new features that allow compilers to take a proactive role in exploiting instruction-level parallelism (ILP). Studying on software pipelining for IA-64 architecture is important for achieving the overall performance of IA-64 platform.In this thesis, we discuss the issues on loop unrolling, loop scheduling scheme, data prefetching, etc. The main contributions are:(1) A method for selecting loop unroll factors in SWP. By selecting reasonable unroll factors, the performance of loop unrolling is improved.(2) A heuristic for selection of loop scheduling methods. Both SWP and list scheduling have their advantages and disadvantages. SWP should be applied only when its benefit outweighs its overhead. Thus the performance degradation due to undirected SWP is avoided, and the performance of SWP is improved.(3) A method for solving the problem of insufficient static registers in SWP. By utilizing spare rotating registers instead of static registers, more loops are allowed to be optimized through SWP.(4) A method for reducing redundant data prefetching instructions in software pipelined loops. By utilizing rotating registers, redundant prefetches are minimized. The overhead of data prefetching is reduced and the program performance is improved.(5) Hardware-supported data dependence relaxation (HSDDR). Software pipelining of loops with conditional statements remains a challenge. Current algorithms fail to solve concurrently two problems: worst-case constraints and path combination. HSDDR is proposed to do so. The key ideas are: (1) datadependence relaxation, which frees loop form worst-case constraints; (2) predication execution, by which code expansion due to path combination is avoided. A simplified compilation and simulation system is implemented. Preliminary experiments indicate the correctness and effectiveness of the proposed technique.