Research On Software Pipelining Techniques For EPIC Architectures

EPIC defines a new style of architecture that enables higher levels of instruction level parallelism (ILP) without unacceptable hardware complexity. Software pipelining is a loop scheduling technique that extracts ILP by overlapping the execution of several consecutive iterations. Although studying of software pipelining has been made for over twenty years, it is still a difficult problem to improve the performance of software pipelining by utilizing new architecture features. In the dissertation, we discuss the issues on loop unrolling, register allocation, and cost model, etc. Some of the achievements are applied to the implementation of an open source compiler.The contribution of this dissertation includes:(1) A register sensitive unrolling (RSU) algorithm is presented, which evaluates unrolling factors considering register pressure to allow more loops to be software pipelined;(2) A stacked register allocation (SRA) algorithm is presented to allocate free stacked registers to variants requiring static registers. The novel mechanism dynamically participates register functions, as well as overcomes static general register pressure for software pipelining;(3) A cost model for software pipelining is proposed in the dissertation, and quantitative evaluation is also performed;(4) A dependence based cost testing (DBCT) algorithm and decision framework are proposed. The main idea is to apply software pipelining techniques to loops only when performance potentials are identified;(5) The design and implementation of an open research compiler (ORC) is studied. Some research achievements are involved in it and released in ORC 2.0.