| The explosive growth of cellular, cordless, and PCS applications has resulted in a need for higher levels of system integration in order to achieve low costs, small size, and low power dissipation. To address this need, recent efforts have been focused on the development of a single chip transceiver using CMOS technology. Direct conversion receiver architecture is advantageous since it eliminates the need for off-chip filters. A fully-integrated frequency synthesizer is an important part of the transceiver system, because it affects the sensitivity of weak signals in the presence of strong interference.; This thesis describes the design procedure of a CMOS PLL frequency synthesizer suitable for CDMA receivers. The research explores the use of a novel bond wire VCO with automatic compensation for bond wire inductance variation and the adaptation technique to meet low phase noise, fast settling and low power consumption requirements. An experimental prototype has been implemented in a 0.18 mum CMOS technology. At a 1.8 V supply voltage, the PLL frequency synthesizer has a low power dissipation of 24 mW. The simulation results show that the phase noise of the synthesizer is -121.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 mus. |
