| While the CMOS processes move to the nanometer regime and become more "digital" in nature, the consumer demands continue to focus on power-efficiency and reconfigurability. The optimal solution no longer lies only in the circuit design space. One has to consider architecture changes and look at the system as a whole. This thesis presents four such case studies.;The multi-rate Sigma-Delta ADC proposed in this thesis, is at its heart a multi-stage traditional Sigma-Delta ADC where the first stage is running at `N' times the sampling frequency. As `N' tends to infinity, this approaches a hybrid Sigma-Delta with a continuoustime(CT) front-end(FE). Thus, the new architecture exploits the best of both worlds---discrete and continuous. It has the clock-rate to power trade-off advantage of a discretetime(DT) Sigma-Delta. It also has anti-aliasing feature similar to the continuous-time(CT) Sigma-Delta without its sensitivity to clock-jitter and EMI.;In a similar architectural optimization, the position of the zeros of the noise transfer function (NTF) of a traditional Sigma-Delta converter is altered by modifying the loop filter to create an N-Tone Sigma-Delta converter. If the signals are then placed only in these noise valleys---a MC-OFDM, for example---a high signal-to-noise Ratio (SNR) can be achieved. In its most simplest form---the number of noise valleys being one---the N-Tone Sigma-Delta converter reduces to the familiar band-pass Sigma-Delta converter.;A low-power three-lane 231 -1 pseudo-random binary sequence (PRBS) generator is realized by multiplexing four appropriately delayed parallel sub-sequences running at one-fourth the data rate. The prototype achieves its low-power by amortizing the power of the PRBS core over the three lanes and by carefully partitioning out the overall architecture into CMOS and CML circuit spaces.;Finally, a cost-effective low-jitter clock-distribution in a noisy environment is realized by making use of the well-known T-line clock distribution schemes on-die and moving the power distribution for the clock-network into the package. |
