Research And Implementation Of DWA Algorithm Applied In Sigma-delta ADC

By adopting oversampling technique and noise shaping, sigma-delta ADC can achieve high resolution, and has been widely used in digital audio, Integrated Services Digital Network and digital telephone systems. Improvement in digital communication systems as well as popularity of portable systems has increased the demand for broad-band, high-resolution, low-power analog-to-digital conveners over the past few years. For such applications, the sampling rate of modulator can’t be too high. In order to meet the requirement of high-resolution, multibit quantization technique could be adopted. The DAC of sigma-delta modulator with multibit quantizer is also multibit. The multibit DAC would introduce nonlinearity error, which should be optimized by digital correction technique. Currently, the more popular digital correction techniques are DEM(Dynamic Element Matching). The most commonly used DEM techniques are ILA(Individual Level Averaging), Randomization, DWA(Data Weighted Averaging) and so on, of which the most practical and simple technique is DWA algorithm. This dissertation is mainly concerned with the research and design of DWA algorithm applied in sigma-delta ADC. The main achievements are outlined as follows:1. Simulation result with MATLAB modeling show that the two-order three-bit modulator with DWA algorithm is 20.5d B higher than the two-order three-bit modulator with Thermometer code in SNDR, and that the two-order three-bit modulator with DWA algorithm is 8.4d B higher than the two-order one-bit modulator in SNDR. This prove that the mismatch noise created by multibit DAC is first-order shaped by DWA algorithm, that the resolution of modulator is improved by reducing in-band harmonics, and that the three-bit modulator with DWA algorithm is superior to one-bit modulator.2. The circuit of DWA algorithm is designed in Verilog HDL which is verified with Modelsim. The several basic processes of logic synthesis using TCL scripts is systematic studied. The RTL level Verilog code is compiled to netlist with DC(Design Compiler). The synthesis process is automatically implemented using TCL scripts. The report after synthesised shows that the DWA algorithm circuit meet design requirements, and that the circuit is only 467032?m in area.3. Based on the TSMC 0.18 ?m process, the circuit of DWA algorithm is physical designed with Soc Encounter. Power ring and power stripes is added for stable power supplying to the chip in Powerplan stage. Trial Route is implemented after Placement to to quickly assess the quality of Floorplan and Placement. The clock network is specially processed in double spacing and wire shielding after clock tree synthesis to reduce the impact of crosstalk. The impact of crosstalk and PAE(Process Antenna Effect) is considered in routing stage, and the methods of repairing crosstalk and PAE is studied. The final verification results meet design timing, crosstalk and PAE requirements after detail routing. The circuit operating at 50 MHz in frequency. The total power consumption of the circuit with power supply of 1.62 V is 4.76 m W.