Hardware software co-design of a resource efficient coarse grained reconfigurable architecture for high throughput media processing applications

Modern media processing applications require architectures that deliver extremely high throughput. The recent increase in demand for portable multimedia processors has placed a strict constraint on the total power and area budget of these systems. Moreover, as these DSP algorithms continuously evolve and increase in complexity, it is necessary for the architectural solutions to be extremely flexible so as to effectively adapt to this rapidly evolving application domain. Over the past two decades, reconfigurable architectures have emerged as ideal platforms to cater to this niche category of applications and algorithms.;Traditional reconfigurable solutions have been primarily based on the use of Field Programmable Gate Arrays (FPGA) to cater to digital signal processing (DSP) algorithms. FPGAs, often classified as fine grained solutions, provide easy reconfiguration, simple programming-compilation, and hence, extremely low time to market. This combination of flexibility, reusability and more importantly, reduction in design and testing time makes them ideal low cost reconfigurable solutions, far better than application specific integrated circuits (ASIC), for servicing the continuously evolving domain of media processing. However, FPGAs provide only bit-level granularity resulting in significant routing and control overhead when mapping algorithms. Furthermore, even though FPGAs provide ease of programming through their use of conventional hardware description languages (VHDL, Verilog), in order for an architecture mapped on them to extract maximum throughput, strict design constraints have to be adhered to. As a result, recently, coarse grained reconfigurable architectures (CGRA) have received increased attention as better solutions for computationally intensive DSP and media processing algorithms.;This work describes the author's contribution in the hardware software co-design and evaluation of resource-efficient coarse grained reconfigurable architectures for high throughput media processing applications. As part of this research, two new reconfigurable architectures MORA (Multimedia Oriented Reconfigurable Architecture) and ReVAMP (Reconfigurable Variable Precision Architecture for Media Processing), which provide 8-bit and 8-16-32-bit granularity respectively, are presented. The architectures were developed with the objective of maximizing the resource and cost efficiency when performing popular media processing algorithms, while at the same time maintaining relatively higher throughput per resource compared to competing adaptable solutions proposed in the same time-frame. Considering the potential applications of the architectures beyond media processing, particularly in encryption and space electronics, low-overhead methods to radiation harden them were also explored and are presented in this thesis.;To estimate the optimum mix of resources as well as the feasibility of design decisions, detailed cost models were developed during the course of this research work. These models include and incorporate the costs incurred at various stages during the design cycle of the product and also factor-in the cost-amortization over the life-cycle of the product, and are presented as an effort to feed into the design cycle of the next generation reconfigurable architectures.;Finally, recommendations about future work especially in the areas of circuit and device optimization have been presented to ensure the survival of reconfigurable architectures beyond the conventional-CMOS era.