| Advances in integrated circuit technology have fueled microprocessor growth for the last fifteen years. In addition to higher clock rates, each increase in integration density offers new opportunities for microarchitectural innovation. We propose that a multiprocessor microarchitecture is a better use of these silicon resources than the current trend of support for increasingly wider instruction issue. In general, we find that applications that exhibit significant amounts of instruction level parallelism also exhibit parallelism at higher levels that can be more efficiently exploited by a multiprocessor microarchitecture. In order to support both fine and coarse-grained parallelism, we propose the use of a shared second-level cache to allow for the efficient sharing of data between individual processors on a single chip.; In making the case for a single-chip multiprocessor, we evaluate a wide range of hand and compiler parallelized applications and multiprogramming workloads. However, there are many integer applications written in C which are not easily parallelized by hand, and can not be automatically parallelized by a compiler due to the inherent problems in pointer disambiguation. For these applications, we describe a model that supports speculative memory accesses and dynamically detects dependency violations. This relaxes the constraints placed on the compiler since it no longer has to statically guarantee that the generated code is free of dependencies. Results from this model indicate that significant speed-up is possible on C applications with minimal increases in the processor's memory state. |
