Design Of LC CMOS Voltage Controlled Oscillator

With the rapid development of the wireless communication technology, the market arises great demond for radio frequency (RF) integrated circuits (ICs). Because of the mature technology, low cost and low power consumption, CMOS RFIC becomes the development trend of RF ICs. The Voltage-Controlled Oscillator (VCO) holds a very important position in RFICs, which is the main part of PLL, clock recovery circuit and frequency synthesizer. VCO is the bottleneck in CMOS RF ICs because of the random fluctuation shift and phase noise at output frequency. The low quanlity factor (Q) of spiral inductor on silicon (SIOS) is the key point to affect VCO's performance.In this paper, heories and practice of LC VCO are studied; the theory of CMOS negative resistance VCO used in Phase-Locked Loop is analyzed. The thesis introduces the method of "One-port Oscillator" analysis, compares the performances and characteristics of different kinds of "negative-Gm" oscillators. And a 1.4GHz LC VCO has been successfully designed.Since the fully integrated inductors with high quality factor are the key of a LC VCO design in CMOS technology, the structures and realizations of on-chip spiral inductor in CMOS technology, the methods of inductor modeling, and the physical reasons which affects the Q-factor are analyzed. Then we introduce the realization in CMOS technology of varactor, which is the other passive component in LC VCO. And the simulations have been done in Cadence.We have studied two analysis methods of phase noise: linear time invariant and nonlinear time invariant. The phase noise theory of oscillator is studied in detail, including Leeson Quasi experimental Model and Impulse Sensitivity Function (ISF). The characteristic of different area's phase noise can be successfully explained by these two methods. Several methods are given for lower phase noise. These methods are applied in an actual VCO and are proved to be effective.Circuit simulation, layout design, extraction of parameters and post layout simulation have been done in Cadence for the LC VCO design in this thesis. The simulation result shows the oscillation frequency is adjustable, and the range for adjusting is 1.33GHz～1.44GHz when control voltage change from OV to 1.8V, the phase noise at 10kHz,100kHz and 1MHz offset are -82.85dBc/Hz, -110.7dBc/Hz and -134.2dBc/Hz respectively.