| Future multiprocessor systems-on-chip (SoC) designs will need novel on-chip communication architectures that can provide scalable and reliable data transport—On-chip network architectures are believed to be the ideal solution to many of today's SoC interconnection problems. On-chip network architectures may adopt design concepts and methodologies from computer networks, namely from system-area-networks and parallel computer clusters. Nevertheless, silicon implementation of networks requires a different perspective, because network architectures and protocols have to deal with the advantages and limitations of the silicon fabric. These characteristics will require new methodologies for both on-chip switch designs as well as routing algorithm designs. We envision that future on-chip systems will be communication-centric, in particular, energy and performance issues in designing the communication infrastructure will become challenging.; In this thesis, we explore several critical aspects in the physical and network layers of the on-chip communication stack that include: (1) On-chip interconnect power consumption modeling and simulation. (2) On-chip routing schemes and switch architecture. (3) Packetization and its impact on system performance and power consumption. (4) Physical planning for on-chip networks. Many of the issues are new and unique for on-chip networks, thus novel techniques and design concepts have to be explored.; Using multi-processor systems-on-chip (MPSoC) networks as the experimental platform, this thesis presents both quantitative and qualitative analysis for on-chip networks. New methodologies and solutions are also proposed to achieve better performance and power balance for MPSoCs. |
