| With the advent of deep sub-micron technology, System-on-Chip (SOC) architectures are becoming possible for a range of applications. However, as single chip systems become a reality, ingenious solutions are needed for many arising architectural issues. One such issue is the design of an on-chip interconnect to facilitate communications among different IP blocks. The integration of multiple cores on a single die has signaled the beginning of a communication-centric design philosophy rather than a computationally centered one. Further, the introduction of nanoscale technology has emphasized the importance of a communication-conscious design where global wiring delays do not scale down as fast as gate delays in newer technologies. Therefore, on-chip interconnections are expected to be a major hurdle in the design of embedded SoC architectures and high-performance multicore architectures alike. While there is a large body of literature on traditional multiprocessor architectures, the design and analysis of an on-chip communication infrastructure is inherently more complex because of its resource constraints, floor planning, and technology scaling artifacts. Consequently, to resolve the growing concerns of on-chip communication behavior, new architectural and technological solutions are being vigorously investigated. Among the architectural trends, use of on-chip packet-based communication networks, known as Networks-on-Chip (NoC), have been gaining wide acceptance due to their scalability. These NoCs have been deployed in current commercialized products, including a recently announced 80-core TERAFLOP processor [1]. While NoC research has made significant progress, there is still the lack of a generic design methodology which encompasses issues in performance, scalability, power, and reliability in a cohesive fashion.; This research consists of five parts. First, the design and analysis of NoC micro-architectures has been explored, where a comprehensive platform for evaluating the performance and energy consumption behavior has been developed. This framework allows for investigating the scalability issues of these NoC architectures as well as provides a means by which different system configurations, wiring layouts, switching mechanisms, routing algorithms and micro-architectural designs could be evaluated. The rapidly increasing use of SoC architectures has accentuated the need for efficient on-chip communication infrastructures. Thus, as the second part of this work, we proposed one type of solution, in which a low-latency on-chip router architecture supporting adaptive path-sensitive mechanisms, was shown to be able to minimize average packet latency by intelligent path selection and reduced switching activities. Third, we have developed an analytical model. Another fundamental aspect of NoC design is the ability to precisely and efficiently provide analysis of an NoC's performance, fault-tolerance, and energy behavior. We developed a queuing-theory-based analytical model for NoC architectures which performed latency and power analysis at the granularity of individual hardware sub-modules, resulting in an increase of the models accuracy. The model developed here quantified the overall power consumption by capturing the utilization of different component and their corresponding energy consumptions. By integrating performance, power, and reliability models, the analytical model was further able to evaluate multi-objective tradeoffs. Fourth, as a comprehensive design paradigm, we proposed a novel, fine grained modular router architecture utilizing a Row-Column Decoupled (RoCo) design. We explored the SoC/NoC design space for reliable and predicatively high-performing architectures, and developed suitable fault-tolerant techniques to handle permanent hard faults. This architecture comprised of a powerful amalgam of novel techniques, all of which work in unison to produce a very efficient and fault-tolerant interconnection system. T... |
