| Network-on-Chip (NoC) has been suggested as the communication resource to overcome the on-chip physical interconnect issues for complex System-on-Chips (SoCs). Router and network interface are the two of the key components of the NoC. The costs (area, power) and the performance of an NoC depends on the router architecture. Also, to facilitate SoC based designs, simple and generic network interfaces with minimal overhead are required to integrate IP (Intellectual Property) cores with diverse communication requirements in plug and play fashion. How to achieve the high performance, meanwhile, reducing the power and area consumption, is the new challenge of designing NoC in the future. This work focuses on the modeling and analysis of router and network interface architectures. Analysis on performance, power, area and configurability on the architecture level is done for alternative router and network interface architectures. |
