Networks-on-Chip based high performance communication architectures for FPGAs

Networks-on-Chip is a recent solution paradigm adopted to increase the performance of multi-core designs. The key idea is to interconnect various computation modules (IP cores) in a network fashion and transport packets simultaneously across them, thereby gaining performance. In addition to improving performance by having multiple packets in flight, NoCs also present a host of other advantages including scalability, power efficiency, and component re-use through modular design.;This work focuses on design and development of high performance communication architectures for FPGAs using NoCs. Once completely developed, the above methodology could be used to augment the current FPGA design flow for implementing multi-core SoC applications. We design and implement an NoC framework for FPGAs, Multi-Clock On-Chip Network for Reconfigurable Systems (MoCReS).;We enable the routers to function at independent clock frequencies, that are dictated by the FPGA place & route constraints, and yet follow a low latency virtual cut-through flow control. With increasing design complexities, power trade-offs play a significant role in FPGA design. We analyze the power consumed in the NoC framework that we have developed on a Virtex-4 FPGA. Through experimental results, we study the various components of power consumed in an FPGA based NoC.;We propose a novel micro-architecture for a hybrid two-layer router that supports both packet-switched communications, across its local and directional ports, as well as, time multiplexed circuit-switched communications among the multiple IP cores directly connected to it. Results from place and route VHDL models of the advanced router architecture show an average improvement of 20.4% in NoC bandwidth (maximum of 24% compared to a traditional NoC). We parameterize the hybrid router model over the number of ports, channel width and bRAM depth and develop a library of network components (MoClib Library).;Synthesizing an NoC topology for FPGAs from the above library of network components requires a complex trade-off among switch complexity, area available and bandwidth capacity. We develop an algorithm and an application-generic design flow that includes required bandwidth and area in the cost function and synthesizes the NoC topology for FPGAs. For a set of real application and synthetic benchmarks, our approach shows an average reduction of 21.6% in FPGA area (maximum of 26%) for equivalent bandwidth constraints when compared with a baseline approach.;Interconnecting IP cores along with our NoC requires a glue logic that can connect different versions of the router to IPs. To accomplish this, we design a customizable Network Interface that is compatible with our 2-layer hybrid router. Towards capturing real core implementation effects, we characterize a library of soft IP cores and implement a typical image compression application on our FPGA. Through experiments we determine the area and power overhead of our on-chip network on an FPGA when implemented along with a typical application. Further by accurately modeling our On-chip network for area, delay and power, we develop a platform that could be used to floorplan a complete multi-processor application along with the NoC.