Correlation-aware statistical timing analysis with non-Gaussian delay distributions

Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The existing linear delay models are insufficient to handle the continuously increasing process variability. Moreover, the non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever.; In this thesis, we first build quadratic delay models for industrial standard cell libraries. With the new models, we then present an efficient block-based statistical timing analysis approach with linear complexity with respect to the circuit size, which can accurately predict the non-Gaussian delay distributions from realistic nonlinear gate and interconnect delay models. This approach accounts for all correlations, from manufacturing process dependence to the re-convergent circuit paths to produce more accurate statistical timing predictions. With this approach, circuit designers can have increased confidence in the variation estimates, at a low additional computation cost.; Besides yield predictions, Critical Path Analysis is always an important task in timing verification. Critical paths and critical gates can help circuit designers to optimize circuit performances. Since process variability can change the criticality of long paths, statistical approaches should be incorporated into Critical Path Analysis.; To address this problem we have developed two novel techniques that can efficiently evaluate path criticality under statistical non-linear delay models in this thesis as well. They are integrated into our nonlinear block-based Statistical Timing tool with the capability of handling arbitrary correlations.; Experiments on ISCAS85 benchmarks as well as industrial circuits prove both accuracy and efficiency of our statistical timing analysis and statistical critical path analysis approaches.