Study On Timing Characterization Analysis Method Considering Global False Path Of SoC

The development of semi-conductor technology has made the scales and performance of the integrated circuits reach an unprecedented stage from the electronic circuit unit with single function to SoC (system on a chip). In the developmental process of the integrated circuit, one of the most important aspects in high performance electronic circuit is timing characterization analysis. Along with the development of the manufacture craft technology of chips towards VDSM (very deep sub micron) domain, the influence of interconnect delay becomes greater and plays a decisive role in circuit delays. At the same time, the enhancement of operating frequency in chips make the cycle time close to the circuit delay. The timing tolerance of the high performance circuit becomes more and more slight, thus raising a higher requirement for timing analysis and the building of delay models for each part of the circuit. How to build up timing analysis models with dissimilar precisions and complexity in different phases is one of the key problems that need to be resolved in SoC design.At present, topological analysis is commonly used for timing characterization analysis purpose. But it has the serious deficiency of ignoring false paths, thus topological analysis can lead to overly estimation of timing models. A solution was proposed which takes advantage of mode dependency. This method isn't able to detect false paths of the whole circuit generated by connections between modes. The method proposed in this paper precisely addresses this problem. As we show in this paper, path delays of circuits can also vary significantly. In previous methods, too huge delay over-estimation occurred because we considered only local false paths not global false paths generated by connections between modes. For more accurate timing analysis we take the mode dependent characterization approach further and apply the notion of the global false path, the functional delay analysis between modes to a previous timing analysis of circuits and propose a...