Statistical timing analysis for digital circuit design

When the device size in digital circuits scales down to nanometer region, the parameter variation will significantly affect the circuit performance and the traditional corner-based timing analysis methods are often too pessimistic to accommodate increasingly aggressive design goals. Statistical timing analysis, which models the parameter variation statistically, becomes a promising variation-aware solution for the digital circuit design at the nanometer era.;The first difficulty of statistical timing comes from the numerous types of timing variable correlations caused by inter-parameter dependency, parameter's spatial dependency, circuit's path reconvergence and the coexistence of transparent latches and feedback loops etc. We construct a comprehensive statistical timing framework to include all of these correlations to improve the timing accuracy. The second difficulty of statistical timing comes from the non-linearity of the timing analysis and the non-Gaussianity of the timing variables. We also propose algorithms to deal with these non-idealities inside our statistical timing framework.;Eventually, statistical timing analysis will take inputs from the manufacturing parameter measurements and generate outputs of timing predictions to the post-silicon delay testing. To complete such a timing flow, we firstly propose a quadratic fitting method to generate the input parameter models from measurement data. We also propose a linear prediction model which combines the statistical timing and delay testing results to provide circuit performance estimation while reducing the testing cost.