Current-based test in deep sub-micron environment

Integrated circuit test strategies and their implementations have been driven by the trade-off between a test cost and its effectiveness. Technology trends in the semiconductor industry enabled manufacturing of a transistor device with a dramatically reduced feature size, which provided a foundation for the exponential increase in densities, complexities, and frequencies of integrated circuits. These trends, however, presented more complex test environments which resulted in degraded quality of the conventional specification or fault-model-based test methods and a significantly higher manufacturing test cost.; Current-based test has been an important failure analysis and characterization tool, indispensable for test quality improvement, test cost reduction, and burn-in elimination. Highly integrated deep sub-micron technology processes, characterized by the exponential increase of leakage currents as well as reduced control over process variations, render existing current-based test methods less effective with constantly declining capabilities. Most notable challenges arise from the difficulties to access deeply embedded circuits, perform accurate and fast current measurements, and process the signals so that useful information could be extracted and interpreted for the test purpose.; This thesis investigates the application of the current-based test methodology for digital and analog circuits in a deep sub-micron environment. A built-in current monitoring solution has been identified as a strong opportunity to address the challenges by enabling easier access to an embedded core. A topology of the versatile CMOS current sensing device is proposed as a built-in self-test monitor for conventional digital/analog IDDQ power supply current test. A novel sensor topology is successfully employed in a current monitoring testing scheme. The presented sensor is a scalable and practical embedded solution for high-frequency parametric IDDQ test of standard CMOS integrated circuits.; A feasibility of a structural model-based method for testing analog integrated circuits has been explored. The proposed method is an extension of digital IDD test to analog circuits. We investigated the detection rate based on the resistive open and short fault model within a MOSFET device. Input test signals are optimized for maximum detectability of introduced faults. The stimuli required for defect screening are DC signals which can be easily produced on-chip. This simple yet effective method is suitable for production testing, as a preliminary and complementary test of embedded analog circuits for early defect screening in highly integrated environments.