Thermal-aware design and analysis techniques for integrated circuits and high-performance microprocessor systems

Physical phenomena such as temperature and power have an increasingly important role in performance and reliability of modern process technologies. This trend will only strengthen with future generations. In this dissertation we present mechanisms for thermal management and power optimizations of integrated circuits.; We present three thermal aware high-level synthesis techniques for peak temperature reduction targeting ASIC design flow. Decisions made during high-level synthesis impact the activity of functional resources and their power consumption. Power consumed is dissipated as heat. The first approach consists of two constructive temperature-aware resource allocation and binding algorithms - temperature constrained resource minimization and resource constrained temperature minimization. The second technique is an iterative temperature aware binding algorithm, which evenly distributes activity across functional units. The third mechanism combines temperature-aware scheduling and binding based on feedback from post floorplan thermal simulation. Our techniques are effective in peak temperature reduction, and reducing leakage and total power consumption.; In order to maintain performance per Watt in microprocessors, there is a shift towards chip level multiprocessing paradigm. With such large-scale integration and increasing power densities Dynamic Thermal Management (DTM) continues to be a significant design effort to maintain performance and reliability. We present two mechanisms to perform real time frequency scaling as part of dynamic frequency and voltage scaling to assist DTM. The results show that our algorithm, by incorporating physical interaction of the cores, consistently succeeds in maximizing the operating frequency of the most critical core while successfully relieving the thermal emergency of the core. DTM techniques rely on accurate readings of on-die thermal sensors. Next, we present novel techniques for determining the optimal locations and allocations for thermal sensors to provide a high fidelity thermal profile of a complex microprocessor system. We show that our tool is able to create a sensor distribution for a given microprocessor architecture providing accurate thermal measurements.; Increased logic density and programmability of FPGAs cause high power dissipation and on-chip temperature. We present techniques for placement and minimization of sensors, which can then be mapped onto FPGA, post-fabrication for thermal monitoring and power driven netlist partitioning for realizing low power FPGAs.