Research Of The Test Generation Algorithm For The Digital Integrated Circuit

Digital integrated circuit is one of the quickest techniques in development. With the development of the design for the digital integrated circuits and the technique of craft, the scale and the complexity of the digital integrated circuits become more and more large, and the test generation for the digital integrated circuits is becoming increasingly difficult. It has become the bottleneck for the production of integrated chip. The traditional test generation algorithm is inefficient for the VLSI circuits. So the research of new and effective test generation algorithms has very important value and meaning. The problem of test generation for the digital integrated circuits is a hard solved problem in mathematics ,because it is a NP-completeness problem, which has been proved. Although many test generation algorithms have been proposed in the last few years, there is no one that is efficient for all VLSI circuits. The problem of test generation for the digital integrated circuits has become an important research subject. The test generation for the digital integrated circuits is selected as research target in this paper. The single stuck-at fault model and the path delay fault model are used. It mainly aims to improve the fault coverage and reduce the test generation time. The main contents are as following: 1.　The development and current research status of the test generation for the digital integrated circuits is introduced in this paper. The existing problems and future direction for development are pointed out. 2.　The test generation algorithm based on Hopfield neural networks for combinational circuits is studied, three-valued neural networks is applied in the test generation and the test generation algorithm based on three-valued neural networks for combinational circuits is proposed in the paper. Representing digital circuits by three-valued neural networks may reduce research space and avoid many wasteful assignments. So three-valued neural networks'application in combinational test generation may reduce test time and improve test efficiency. The test vectors for fault can been obtained by constructing the constraint network of the circuits and solving the minimum of energy function of the constraint network. 3.　The test generation algorithm based on Boolean difference for combinational circuits is studied. Considering that there is a lot of exclusive OR calculation in the Boolean difference, a simplified method that solves first order Boolean difference in the course of generating test vectors for single stuck-at fault in combinational circuit is proposed. In this method, test vectors for combinational circuit can be obtained only by solving an identity and exclusive OR calculation is not needed. The simplified method of second order Boolean difference is obtained by analyzing the second order Boolean difference, and it provides convenience for the test generation of two faults in the combinational circuit. 4.　The test generation algorithm for non-robust path delay fault in combinational circuits is studied. There are many faults in digital integrated circuit, one of which is delay fault. The circuit can't work properly at high-speed clock frequency if there is delay fault in the circuit. So it is very important to study the test generation for delay fault. Until mow, many delay fault models have been proposed by scientists, the path delay fault model is one of the most general models among them. However, the disadvantage with the path delay fault model is that the number of faults with respect to the number of gates in the circuit is exponential, and generating test vectors for faults in short time is generally hard. We will generate test vectors for non-robust path delay fault using stuck-at fault test generation algorithm by using path-leaf transformation. This algorithm can avoid "exponential problem", reduce test generation time and improve test generation efficiency.