| Facing increasingly critical constraints, it is more and more difficult for synchronous integrated circuit (IC) designs to satisfy design goals. IC designers require new technology to address the challenges in power, performance, and area. Asynchronous paradigms, such as the NULL Convention Logic (NCL), will become a necessity in tomorrow's semiconductor industry. NCL technology has already demonstrated significant improvements in key issues such as energy consumption compared to synchronous counterparts. Applying the Multi-Threshold power reduction technique on NCL design has raised new prospects regarding energy saving. To evolve in the future, it is important for this technology to reveal its tradeoffs among energy, speed, and area.;This thesis work analyzes the power and timing constraints of the Multi-Threshold NCL (MTNCL) library and divulges by simulating an optimum energy-delay configuration using transistor sizing for each of the 27 threshold gate of the MTNCL library. Results show that new optimized gates deliver on average four times faster speed while only consuming less than two times the energy of the minimum-size transistor designs. |
