Performance Improvement Of GeSn Tunneling Field-effect Transistor Enabled By Strain Engineering And Heterojunction

Tunneling Field-effect Transistor(TFET) can achieve 60 mV/decade subthreshold swing(SS)at room temperature, and exhibit a higher drive current compared to the conventional metal-oxide semiconductor field-effect transistor, at a very low supply voltage. Hence, TFET has been considered as a candidate structure to realize integrated circuit with ultralow power consumption. Currently, GeSn based TFETs have become a hot spot in the research of microelectronic logic device. The bandgap of GeSn alloys at Γ point is tuned from 0 to 0.8 eV. As the Sn composition increases up to 6.5~11%, indirect to direct bandgap occurs in the materials. Bases on these properties, GeSn TFETs have demonstrated the improved electrical performance compared to other group IV alloys devices and even III-V TFETs. In this paper, we carried out a thorough theoretical analysis on the improvement effects of tensile strain and heterojunction on the electrical performance of GeSn TFETs.In this work, the impacts of strain on the energy band structure and carrier effective mass of GeSn alloys were investigated in details using k?p theory and empirical pseudopotential method(EPM). The electrical performance of strained and relaxed GeSn TFETs was simulated and analyzed based on the non-local Kane’s model. The results demonstrate that band to band tunneling generation rate GBTBT and drive current of GeSn TFETs can be improved by inducing tensile strain into the device. We also find that this boosting effect of strain is related to the surface orientation of devices. Based on the non-local EPM, the full band structures of GeSn and SiGeSn were calculated. GeSn heterojunction enhanced TFETs(HE-TFETs) were designed and characterized. It is found that the distance between source/channel tunneling junction(TJ) and the Ge1-xSnx/Ge1-ySny type-I heterojunction, LT-H, has a significant influence on the device performance, which can be improve by optimizing the value of LT-H. Theoretical analysis indicates that the presence of the heterojunction leads to the shortened tunneling path, enhancing the GBTBT and tunneling current of the transistors. In this work, TFET with GeSn/SiGeSn type-II hetero TJ was also designed. By tuning the alloy compositions, type-II heterostructure and lattice matching can be obtained at GeSn/SiGeSn interface. GeSn hetero-TFETs achieve a significant improvement in electrical performance compared to the homo transistors. By extracting the carrier distribution in the devices, we can observe that the type-II TJ can effectively enhance the carrier density near the TJ and steepen the carrier profiles, which contribute to the enhancement in band to band tunneling rate and drive current of GeSn hetero-TFET.