| Tunnel oxide thickness scaling is encountering problem for next generation flash memory device. With tunnel oxide shrinking down, the stress-induced leakage current becomes more serious leading to degraded retention. To overcome this, flash memory with discrete-traps as floating gate was proposed, including nitride charging and nanocrystal storage. The first report on nanocrystal memory is Si nanocrystal memory. After that, tremendous efforts have been put on using semiconductor or metal nanocrystals for memory application. However, for Si, although long retention time has been demonstrated, the long retention is believed to be related to charge storage on defect levels. Those levels are distributed throughout the whole band gap of Si and are not thermally stable, resulting in compromised device reliability. For metals, on the other hand, the band gap is negligible, therefore the issue of defect level charging is effectively avoided. However, the problem with metal nanocrystal memory lies in the reaction or inter-diffusion between metal and tunnel oxide underneath at high-temperature process step, such as source/drain dopant activation annealing for MOSFET. The reaction or diffusion of metal atoms generates weak points in the tunnel oxide, which degrades the device retention.;To solve the dilemma between long retention and scaled tunnel oxide, in this work, engineered floating gate, such as hybrid-nanocrystal and new materials nanocrystals that are compatible with current Si technology, was proposed and good memory performance was demonstrated. Chapter 1 introduces the conventional flash memory, including the operation principle, architectures, challenge in next generation flash memory and some new technologies to address this issue in conventional flash. Chapter 2 describes the methodologies used in this thesis work, including nanocrystal growth methods, nanocrystal characterization techniques, and nanocrystal memory fabrication and device characterization. Chapter 3 discusses the flash memory with Ge/Si hetero-nanocrystals as floating gate. Type-II band alignment between Ge and Si makes Ge/Si hetero-nanocrystal good for long time hole storage than Si nanocrystal memory. In addition to p-MOS, we also developed n-MOS memory with CoSi2-coated Si nanocrystals as floating gate in the Chapter 4. The Fermi-level of CoSi2 locates around the midgap of Si so that the device is good for both electrons and holes trapping. Furthermore, the quantum well formed between CoSi2 and SiO2 is deeper than that of Si and SiO2, leading to an elongated retention time. The Si nanocrystal underneath the CoSi 2 effectively prevents the charges stored in CoSi2 from leaking back to the channel. In order to lower the thermal budget to make silicide nanocrystals, vapor-solid-solid (VSS) growth mode was employed and NiSi 2 nanocrystsals were synthesized as presented in Chapter 5. The long retention of NiSi2 nanocrystal memory is also benefited from the deep quantum well between NiSi2 and SiO2. For next generation flash memory, more uniform nanocrystals with higher dot density, 10 12cm-2, is necessary to meet the requirement of 22nm technology and beyond. In Chapter 6, we developed PtSi nanocrystals using the similar synthesis technique as NiSi2. The nanocrystal density is enhanced from 3x1011cm-2 to 1.5x10 12cm-2.;In short, engineering the nano-floating gate by replacing Si nanocrystals with hybrid nanocrystals and silicide nanocrystals benefits the device retention time. These new memories also exhibit faster programming and erasing speeds. The enhanced memory performance makes the devices fit for next generation memory with further scaled tunnel oxide. |
