Font Size: a A A

Engineering the nanocrystal floating gates for nonvolatile flash memory devices

Posted on:2008-05-31Degree:Ph.DType:Dissertation
University:University of California, RiversideCandidate:Zhu, YanFull Text:PDF
GTID:1448390005451892Subject:Engineering
Abstract/Summary:
Semiconductor nonvolatile flash memory is encountering serious issues in further scaling. Good retention has to be achieved at the cost of slower programming speed. The conventional floating gate device also suffers from serious cell-cell cross talk because of floating gate-floating gate coupling.; Using discrete Si nanocrystal charge storage nodes can solve this problem, driving semiconductor flash memory to further generations. However, due to the semiconductive nature, Si nanocrystal is very sensitive to the structural imperfection/defects. Those defects lead to extra charge traps with trap depth spreading over a large energy range. In other words, the defects lead to many deep traps as well as shallow ones. Those traps are not thermally stable and cause device performance degradation after thermal annealing.; This work is devoted to investigating the feasibility of engineering nanocrystals with a novel structure: Si-based hetero-nanocrystals, to replaces Si nanocrystal for future nonvolatile memory devices. We proposed and simulated Ge/Si and SiC0.008/Si hetero-nanocrystals for p- and n-channel applications in chapter 2. It shows that with Ge/Si or SiC0.008/Si hetero-nanocrystals, the retention time can be significantly improved while the programming/searing speeds remain the same.; Beyond Ge/Si and SiC0.008/Si hetero-nanocrystal memories, a new TiSi2/Si hetero-nanocrystal memory is proposed and numerically investigated in Chapter 3. Different from semiconductor hetero-nanocrystals, metallic TiSi2/Si hetero nanocrystal as floating gate improves not only the retention but also the programming and erasing speeds. Chapter 4 and 5 describe the fabrication of hetero-nanocrystal memory with self-aligned silicidation technique, and characterizations of the fabricated memory devices. Both MOS and MOSFET devices are studied in Chapter 5 with F-N tunneling for charge injection/ejection to/from the nanocrystals. The effort toward the multi-level cell (MLC) application using TiSi2/Si hetero-nanocrystal memory is presented in chapter 6.; The experiments demonstrated that TiSi2/Si hetero-nanocrystal memory possesses superior memory performance than its Si nanocrystal reference memory: faster programming and erasing speeds and much longer retention time.; Therefore, it is concluded that hetero-nanocrystal memory is a very promising candidate to replace Si nanocrystal for future generation nonvolatile flash memory devices.
Keywords/Search Tags:Memory, Nanocrystal, Floating, Gate, Retention
Related items