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Study and Implementation of Lower-Ground CPW Transmission Lines for the Design of V-band Si-based Transceiver Blocks

Posted on:2011-03-28Degree:Ph.DType:Thesis
University:Carleton University (Canada)Candidate:Haroun, IbrahimFull Text:PDF
GTID:2448390002954954Subject:Engineering
Abstract/Summary:
The demand for ultra-high data-rate wireless communication systems and the availability of 7 GHz of unlicensed bandwidth in the 60 GHz ISM band (57-64 GHz) as well as the advances in the CMOS technology, have created a substantial interest in the development of small-size, low-cost millimetre-wave (mmW) systems operating at frequencies in the V-band (50-75 GHz). Although CMOS technology enables having a low-cost system-on-chip that integrates both the analog RF and the digital circuits with the mmW circuits into a single-chip, the technology has design challenges because of its lossy silicon substrate and its process design rules restrictions.;As applications for the implementation of these LG-CPW transmission lines, two key RF building blocks including a 60-GHz band quadrature branch-line coupler and a V-band low noise amplifier have been designed and implemented in a 90-nm RF CMOS process.;The low noise amplifier block utilized LG-CPW transmission lines as matching elements to enable the realization of the needed impedances for achieving optimal noise performance. To the author's knowledge, the amplifier of this thesis is one of the lowest noise figure and the highest gain that have been achieved with a 90nm CMOS technology in the V-band. Also, the power consumption is among the lowest power consumptions of V-band CMOS low noise amplifiers.;The design of the coupler block utilized capacitively loaded LG-CPW transmission lines to reduce the physical size of the quarter-wavelength elements of the coupler. The coupler's size is 0.102 mm2 which is more than 75% size reduction compared to conventional CPW branch-line couplers.;This thesis explores the use of the proposed lower-ground coplanar waveguide (LG-CPW) transmission lines to overcome the limitations of the CMOS technology design rules, which limit the maximum/minimum metal width and the minimum spacing between metal strips. The proposed transmission lines enable the realization of a wide range of impedances that facilitates the optimization and design of V-band passive and active sub-systems without violating the design rules of the CMOS process. Also, they enable achieving low loss transmission line structures.
Keywords/Search Tags:Transmission, CMOS, Low, V-band, Design rules, Ghz
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