Design Of CMOS Front-end Circuit Modules For K-band Receiver

The thesis research the design of RF receiver front-end key circuits, such as low noise amplifier, mixer, and voltage-controlled oscillator, using TSMC 0.18-μm standard CMOS technologyA K-band variable-gain low noise amplifier (VGLNA) is designed using TSMC 0.18-μm CMOS technology. Coplanar waveguide (CPW) transmission lines are adopted as matching elements to reduce the effect of lossy silicon substrate at high frequency. In high-gain mode, the simulated small signal gain of VGLNA is 14.4 dB and noise figure of 2.4 dB at 21 GHz. The gain control range of the VGLNA is 9 dB.A 6-34 GHz distributed drain mixer using CPW technology is demonstrated in this thesis. This MMIC mixer uses a simple distributed topology that is composed of common-source 0.18-μm standard NMOS active device, and it shows a conversion loss of better than 6 dB from 6 to 34 GHz. This distributed mixer achieves low dc power consumption and high linearity for broadband applications.At last, the 22-GHz NMOS cross-coupled push-push VCO using 0.18-μm CMOS technology is design for low phase noise and wide tuning range. The NMOS only cross-coupled pair is used to lower the phase noise, and the simulated 2nd harmonic phase noise is -106.5 dBc/Hz at 1-MHz offset and the frequency tune range up to 8%.