| The demand for higher aggregate bandwidth at all levels of communication infrastructure has been driving research into chip-to-chip communication over short printed circuit board (PCB) traces to its limit, and given rise to chip-to-chip links over short traces on a common packaging substrate or so-called interposer. The latter, referred to as die-to-die communication, is the focus of this thesis. In particular, different interconnect technologies and circuit techniques are explored to maximize the aggregate data rate between chips.;A link model is presented to compare different substrates and die-substrate attachment methods. The model performance is veried against measured results of a 4-4-4 organic substrate and silicon interposer fabricated in a 0.35 um CMOS technology. Using the link model, an appropriate signaling scheme, termination impedance, and interconnect spacing is demonstrated for each technology. Moreover, the maximum achievable data rate is determined over different die-to-die interconnects.;In addition, a prototype single-ended parallel interface is presented. The interface includes a low-power transceiver and a high-density low-cost silicon interposer. The link architecture exploits single-sided and capacitive termination, passive equalization in the transmitter, and CMOS logic-style circuits. The transceiver prototype integrates 3 transmitters and 3 receivers fabricated in 28 nm FD-SOI CMOS technology. The parallel interface operates at 20 Gb/s/wire while consuming 0.30 pJ/bit excluding clocking circuits.;Finally, an overview of the clocking architecture for parallel die-to-die links is presented. A phase rotator is designed and fabricated in 28 nm STM FD-SOI CMOS technology as part of a half-rate wireline receiver which operates at 16 Gb/s. The phase rotator comprises of an Injection Locked Oscillator (ILO) and two pseudo-differential CMOS Phase Interpolators (PIs). |
