| As the lithography process scales the throughput requirement for chip interconnections increases. Furthermore, the band limited channel practically does not scale and the power budget has been more important than ever. This tradeoff has raised the need for innovative designs. As a result plethora of new design techniques has been discussed extensively during the last decade. This challenge prompts the development of the presented work that delivers a complete solution for systems that require low power, high speed and high level of integration.; The proposed work combines the advantages of serial and parallel link architectures, to overcome known problems of both. Parallel links traditionally use binary coding. Their symbol rate is limited mainly due to: reference ambiguity and power supply noise. Serial links on the other hand spend two pins for each link. The proposed coding sends the data differentially among the pins without using a reference signal. In conjunction with a novel driver architecture, it keeps the power dissipation at the transceiver constant, decreasing the power supply noise. The transmitter recycles the current among the drivers to decrease power dissipation, while the receiver uses simple comparators to recover the data.; To demonstrate the proposed coding scheme a parallel link that codes three bits over four conductors was designed in a 0.18-mum CMOS process. It reaches a data rate of 4.2-Gb/s/pin, dissipates 17.1-mW/Gb/s and achieves 100-Gbps/mm2. The efficiency of the coding increases further as it scales. By using only three signal levels the system guaranties that noise margin will remain the same. Using just six conductors the coding scheme sends 5.585 bits increasing the I/O pin efficiency to 93%. The effective bit rate would be 5.2-Gb/s/pin. To further increase performance twelve conductors can be used to code 0.97 bits per pin. |
