Research And Implementation Of High-Performance And Low-Power TCAM

Ternary Content Addressable Memory (TCAM) is a kind of hardware searching engine, which not only can access to data like common memory (e.g. SRAM, DRAM), but also can match and look up data. TCAM is mainly applied as look-up table in core router, data compression, pattern recognition, image processing, etc. The most successful commercial application for TCAM is packet classification in routers. The high search speed of TCAM is due to the parallel comparison operation, which results in the severe power dissipation. As the development of IPv6 and mobile internet, the demand for large-capacity and long-word TCAM gives a challenge to the search speed and power. Many researchers are devoted to reducing the power dissipation of TCAM without sacrificing the search speed.The thesis focuses on the research of high-performance and low-power TCAM. At first, the thesis proposes a TCAM cell with low capacitance of match line, which is in favor of reducing the power dissipation of match line. Compared with other same type cell, the proposed TCAM cell can avoid the short-path power dissipation problem and potential function error. Then the thesis proposes an OR-type cascaded match-line scheme. For the proposed scheme, only the result of match in the previous stage will activate the evaluation of the next stage. Both the small capacitance of pre-charge node in the proposed scheme and the low full-match possibility in the first stage efficiently reduce the power dissipation. In the case of match, the word circuit is equivalent to inverters in series connection, which improves the search speed. After that, the thesis uses Verilog to design a RTL-level TCAM control logic with 8 pipelines, which improves the search speed and throughput capacity of large-capacity TCAM. Finally, the logic synthesis and post synthesis for TCAM control logic are implemented.The proposed 64-wordx72-bit TCAM with 3 stages, based on 0.13-um 1.2-V SMIC process, is implemented. The pre-layout simulation shows that the circuit achieves 0.41fJ/bit/search with 0.48 ns search time. The circuit is implemented in layout with only 97614.14 um2, and the post-layout simulation shows that the proposed scheme realizes 0.58fJ/bit/search within 1.13 ns search time. Adopting the same process, the TCAM control logic is synthesized, which shows that the TCAM control logic can operate at most 400Mhz.