| Many embedded systems today are required to implement security features. These features can range from encrypting communication traffic to securely storing and executing software. In addition to the complexities of implementing such features, embedded systems are also subject to battery life requirements, limited processing power, and the desire for flexibility and extensibility. Traditional solutions to this problem fall into two categories: instruction set extensions and coprocessors. Instruction set extensions can be implemented on synthesizable cores to enhance the performance of cryptographic algorithms. These instruction set extensions usually target specific steps in an algorithm, leaving the majority of the implementation to existing instructions. However, synthesizable cores are traditionally not available for ultra low-power systems. Dedicated security coprocessors, on the other hand, span a wide continuum from very specific peripherals to complete security engines. Coprocessors can increase the performance and energy efficiency of a system while relieving the burden imposed by security algorithms upon the main microprocessor. We study the problem of incorporating AES-256 encryption and decryption in power constrained, low-cost devices such as wireless sensor network nodes. An FPGA-based coprocessor solution was developed using the Actel Igloo that reduces power consumption from a baseline software-only solution of 18 mW to only 0.637 mW. This power reduction is obtained by effectively leveraging the FPGA's on-chip RAM, careful construction of an extremely compact datapath, and the use of a hybrid AES S-Box. |
