Power-aware circuit design and optimization for total chip power reduction

In microprocessor design, power dissipation remains one of the most critical challenges. It requires innovation on all design levels to sustain performance scaling. To provide low-power and high-performance circuits, designers rely on the use of automated circuit design tools. However, existing automated circuit design tools do not guarantee that the optimized (tuned) circuit will operate under minimum power consumption. A new methodology for circuit power optimization called FPR (Free Power Recovery) is developed and presented. As a final result, after using the proposed FPR methodology, the circuit operates at minimum-power for a specified delay target.;The second part of the thesis focuses on evaluating the potential of the proposed circuit optimization for a total chip power reduction. The time-to-market pressures combined with the immense power reduction design space of VLSI design, call for an evaluation of power savings opportunities prior to the investment in design effort. It is important to properly select the circuits with the biggest power savings. In order to do that, the new estimation methodology is developed. The proposed FPR power optimization methodology was implemented in the real industrial chip design environment and incorporated in the tool that every designer was required to use on his/her circuit design in order to reach power optimum design point. The obtained results validate the accuracy of the estimation methodology. The framework presented in this dissertation lends itself to further optimization and refinement, benefiting future low-power high-performance microprocessor designs.