Research On Analog Integrated Circuit Design Methodology And Analog IP Design Technology

Nowadays microelectronic industry has become the biggest one of which production value occupies 4 percent of the whole world. The forecast indicates that its value will reach to 8 percent.Like all the rapidly developing things, development produces division of work and more specific division drive much faster development. The division of microelectronic design industry is also under the way, which is a branch of microelectronic technology. The most attractive one is that design companies grow into two categories—IP (Intellectual Property) block design and system integration. Since the scale of IP block is mainly small or middle, this has a better interface with national design capability and fit for the present situation of our country.IC (Integrated Circuit) design is divided into digital and analog. Design technology of digital IC is widely used in modern electronic system, which drives the advancement of analog IC design technology; consequently, chip can be implemented with more complex functionality, higher speed and reliability. Because automation degree of analog IC design is far from that of digital IC design, analog design depends on the intelligence much more, which makes analog IC design flow and IP design technology face more challenges.This paper first discusses the design methodology of analog IC, namely, analog IC design flow. Based on introduction of mainstream analog IC design flow, this paper presents a new flow in post-layout simulation stage—transistor-level post-layout flow with NanoSim and StarRC-XT.Chapter three and chapter four dwell on analog IP design. For ASIC design of blender controller, in system level, single chip implementation is proposed, which has the advantage of low cost and easy testing; in logarithm level, self adapting correction logarithm is given to compensate frequency inaccuracy of on-chip oscillator by digital cooperation with analog; in transistor level and layout level, design of POR (Power-on Reset) and CZD (Cross Zero Detect) IP are illustrated including layout issues of match and noise. For VCO IP design of PLL chip, it is addressed with emphasis on circuit and layout implementation of four-stage-differential ring oscillator, considering the issues of high gain, high swing and low power dissipation.At the end of this paper, a conclusion is drawn and the prospect of future work is given combined with finished research.