Research On Low Power Mthodology And Implementation For Multipliers In IC Design

With rapid development of IC technologies, power consumption has been a keyfactor for long time, beside speed and area. Currently, low power design is developedfrom basic circuit constitution, try to reduce system power consumption in each stage ofIC manufactory flow, in order to obtain the optimal low power result. The dissertationfollows to such tendency, and focuses to research and design low power methodologyand implementation, at meanwhile, improve some shortages of current low powerdesign. The main work and innovations of this dissertation are as follows:(1) Optimization for the number of addition operation inside multiplierDevelop an encoding methodology for fixed multiplication coefficient, its major isto minimum non-zero bits in optimized coefficient, in order to reduce the number ofaddition operations, which are inside multiplier. Since the methodology reducesaddition operation, rather than decrease system clock frequency and supply voltage, soit does not reduce system efficiency. And, the methodology optimizes internal structureof mulriplier, does not involve any approximation, so it does not cause anymultiplication accuracy loss. In order to test the actual low power effect, a system thatincludes several knids of multipliers is to be the optimization object, the test result is theaverage optimization result of all the intern multipliers, so it is objective, general andactual.(2) Optimization for the width of decimal multiplierAfter error analysis to decimal multiplier, an optimization methodology for decimalmultiplier is developed, its major is reducing the total register bits with maintaining itsoperation accuracy. The methodology can pre-calculate the last-significant-bits in eachaddition operations and omit them directly, these bits will be omited in final calculationresult, so that total register bits of multiplier can be reduced. Because the methodologyonly omit the so call “last-significant-bits”, so it does not cause more calculation error.And it only search all the “1” in coefficient and then excute further operation, so themethodology has advantages of high speed, little resource occupy and easy toimplement. In order to test the actual low power effect of such methodology, aninterpolation filter is optimized by it, its internal logic cells are reduced significantlywithout working characteristics deterioration. Then, a RF circuit is treated as theoptimization object, its optimization result is also meet our expectation. The chapter describe the methodology development from singal multiplier to RF circuit, it has actualreference value.(3) Dual optimization methodologyBase on the2methodologies, a dual optimization methodology is developed, itreduces not only the number of addition operations, but also the width of one multiplier.Firstly, the methodology reduces the number of addition operations, then based on suchoptimization result, it reduces width of each addition once again. From implementationpoint of view, the result of first optimization can be used for the second one, suchimplementation save the computation effort of second optimization, and promoteoperation speed and efficiency of whole methodology. Compared to directly binding oftwo single methodologies, dual methodology has higher working efficiency, and betterlow power result.(4) Implementation solutionTo improve the problem of optimization logic is brought into optimized system,which is existed in present low power design, the dissertation develop a newimplementation technique. By using it, the optimized system has expected low powerresult, at meanwhile, the optimization logic cells are absented in it. For the system thatinclude multipliers, once its characteristics is confirmed, the coefficients of all theinternal multipliers are also fixed, so each coefficient can be optimized in advance, then,the operation is excuted just based on the optimized coefficient after synthesis, thissolution avoid optimized multiplier to include optimization logic cells. Fromsystempoint of view, such solution promote the actual result of methodology.(5) System level low power optimization approachOn system level, based on dual optimization methododlogy and newimplementation solution, plus select different software methodologies and hardwarestructures for different kinds of multiplier. In optimization methododlogy stage, additionnumber optimization is for integer multiplier, dual optimization is for decimal multiplierwhose coefficient is less than one, separately optimization to the integer and decimalparts of decimal multiplier whose coefficient is larger than one. In hardware structurestatge, use series accumulate structure when the count of one in the coefficient is nomore than four, otherwise use cycle accumulate structure. Such approach is system levellow power approach, it promotes system low power result.Through the research of low power technique for multipliers in IC design, inmethodology stage, optimization for addition number and addition width are developed, in implementation stage, a new implementation solution is developed, which canimprove the problem of present low power design, in system application stage, amemthodology and structure selection is developed. The dissertation develop the lowpower technique for multipliers in different stages, it has reference value to IC front-endlow power design for fixed coefficient multipliers.