| Arithmetic operations in binary Galois Fields GF(2 k) play a crucial rule in the area of communications, including error-correcting codes, cryptography, switching theory, and digital signal processing. In these applications, area and speed requirements are essential, therefore an efficient hardware structure for such operations is desirable. The main problems of these applications are their big hardware structure and long processing time. In a way to overcome these difficulties, we propose the use of MVL signals to represent the I/O data signals. In order to do so, we consider the composite Galois field GF((2 n)m) where k = nm . Our composite Galois field is GF((22) m) where we deal with quaternary logic. In our designs, it was important for us to use the same base, which is 2, so that our circuits can replace the one that use the binary field GF(2 k).; In this thesis, we present addition, multiplication, inversion/division, and exponentiation operations in Galois fields using a unique MVL interpretation technique. MVL signals are processed using neuron MOSFETs in voltage mode, which dramatically save in power consumption. We compare the proposed quaternary circuits with the circuits that use the binary field GF(2 k) as their basis. The proposed circuits require much less amount of chip area, less clock cycles to generate the final output result, and are highly regular, thus they are well suited for VLSI applications. |
