Research And Design Of 28-39GHz Continuous Integer Frequency PLL

With the rapid development of 5G technology,CMOS integrated circuits have entered the millimeter wave stage.Therefore,wideband millimeter-wave phase-locked loop(PLL)frequency synthesizers suitable for high-speed systems have become a research hotspot and a difficult point.Although as the size of CMOS integrated circuits goes down,the feature frequency of the devices is increasing,making the device suitable for high frequency design requirements.However,at the same time,the reduction of the supply voltage causes the non-ideal characteristics such as leakage current and noise of the devices to become more significant,which makes the PLL system have complex compromises between high frequency,wideband and low phase noise design.This paper studies and designs a 28-39GHz continuous integer frequency division PLL system,and conducts simulation verification around this hotspot and difficulty.A PLL system typically includes a phase frequency detector(PFD),a charge pump(C.P),a loop filter(LPF),a voltage controlled oscillator(VCO),and a frequency divider.On account of multiple sets of switched capacitors are usually used to realize multiple frequency modulation(FM)intervals in the design of wideband FM VCOs,a fast locking FM interval module is designed in this paper to speed up the locking speed of the system,and this module uses parallel processing to quickly and accurately lock the system to the FM interval closest to the target frequency when the division ratio control bits change.Compared with the traditional processing module,the fast lock FM interval module designed in this paper does not need to perform sequential scan calculation for each FM interval,and does not need to add circuits to distinguish the accuracy of the two adjacent FM intervals that all include the target frequency.The continuous integer frequency division PLL system is designed based on the 1.I v power supply GPDK 45nm CMOS process in this paper.Among the rest,the PFD has a input reference frequency of 100MHz,a phase detection(PD)range of ±1.8?,and a phase death zone elimination time of 158ps.The charge and discharge currents of CP are about 100?A in the output voltage range of 0.1 to IV,the mismatch between charge and discharge current of CP is less than 0.1%.The LPF is implemented based on the third-order low-pass filter,with a bandwidth of about 1/10 of the input reference frequency which is 100MHz,so that the PLL system can be approximately linear system in phase analysis.The VCO is designed based on inductance-capacitance voltage controlled oscillator(LC-VCO),using bits controlled switch capacitors to obtain 8 equally spaced and equal gain FM intervals,to realize the wideband FM with a FM range of 27 to 40GHz,and ensure that the PLL system stably works in the target frequency range of 28-39GHz;Adopting the FM gain compensation circuit,the second harmonic suppression circuit and the bypass capacitor filter circuit to optimize the phase noise performance of the VCO.The frequency divider adopts a high-speed programmable continuous multi-mode frequency divider;The high speed two-divider,which is composed of a front-stage buffer and a back-stage direct injection locking frequency divider,is taken as the input stage,and the 15/16 dual-mode prescaler is realized by combining high speed two-divider,the 16-phasc 8-divider and the phase switching technology;In addition,the 270-400 consecutive integer frequency divider stepping with 1 is realized by combining 15/16 dual-mode prescaler and the Countable counter(PS counter).The PLL system with continuous integer frequency division finally realized in this paper has a input reference frequency of 100MHz,an FM range of 28-39GHz,an FM percentage of about 32.8%,an operating current of about 58mA,and a phase noise of about-106dBc/Hz@10MHz when the output signal frequency is 39GHz.