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Parallel Polar Codes Decoding Algorithm In Free Space Optical Communication

Posted on:2022-04-30Degree:MasterType:Thesis
Country:ChinaCandidate:Y J LiuFull Text:PDF
GTID:2518306338991469Subject:Electronic Science and Technology
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Polar code is a new forward error correction(FEC)technology proposed by Professor erdal Arikan in 2009.It is proved that it can reach the channel capacity limit by strict mathematical methods.It has many obvious advantages,such as low complexity,low delay,error free layer,good short code performance and so on.In this paper,on the basis of in-depth understanding of the principle of polar code coding and decoding,based on Xilinx XCVU13P-FLGA2577-1-E FPGA chip,the adapting multiple code rate CRC-SCL(cyclic redundancy check codes aided successful cancellation list)algorithm with 256 code length is implemented for the first time with a total throughput of 40Gbps.At the same time,the performance of the proposed decoding algorithm is verified in the 56 Gbit/s QPSK(polar-QPSK)back-to-back experiment based on polar code,and the performance of polar code in free space optical communication system is simulated and analyzed.The research work of this paper mainly includes:1)the commonly used code word construction methods of polar codes are analyzed,and the Gaussian approximation method with lower complexity is chosen as the object used in the channel reliability estimation of polar codes in this paper.The common decoding algorithms such as SC,SCL,CRC-SCL and FAST-SSC are studied and implemented.The decoding performance of CRC-SCL algorithm with different code lengths and code rates in white Gaussian noise channel(AWGN)is simulated and analyzed.The simulation results show that the performance of polar codes is better than LDPC codes in QPSK modulation system.2)Based on Xilinx xcvu13p-flga2577-1-e FPGA chip,the high throughput parallel CRC-SCL decoding algorithm with 256 code length is implemented for the first time.The total throughput reaches 40Gbps at the maximum FPGA clock frequency of 156.25MHz.The influence of quantization bits on the decoder is analyzed.Simulation and experiments show that the log likelihood ratio of 8 bits and the path metric of 12 bits are the lowest quantization bits without reducing the bit error characteristics.3)A 56 Gbit/s polar-QPSK back-to-back experiment was carried out.The experimental results show that when the CRC-SCL(L=2)decoding algorithm is used,the BER is 1E-3,and the code rate of 256,512 and 1024 code length polar codes with a code rate of 1/2 obtains 7.5dB,7.9dB and 8.5dB coding gain.Compared with SC algorithm,it improves 0.8db,0.6dB and 0.4db respectively.The CRC-SCL decoding algorithm based on Xilinx XCVU13P-FLGA2577-1-E chip hardware realizes the bit error correction rate of-50.9dBm@1E-3.4)The performance of 25 Gbaud QPSK modulated polar code in free space optical communication system is simulated.The results show that when the transmission distance is 5km and the turbulence intensity is 4,8 and 16,the probability of communication interruption can be reduced by 5.9%,14.5%and 26.7%respectively.When the turbulence intensity is less than 16,the interruption probability of FSO system based on polar code is less than 10%.
Keywords/Search Tags:Polar code, CRC-SCL, Field programmable gate array(FPGA), QPSK modulation, Free space optical communication
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