Interface Design And Verification For SOC Ferroelectric Memory

FeRAM is a kind of high-performance memory,which combines the fast reading and writing of RAM and the non-volatile functions of ROM.It has the characteristics of low power consumption,fast operation speed and strong radiation resistance.Nowadays,it has larger applications in the field of automotive electronics.The AHB(Advanced High Performance Bus)bus is a high-performance bus,and it is also a bus commonly used in today's SoC systems.Its advantage lies in its open bus standard,which can connect different kinds of IP and processors with different performances to achieve communication between them to realize the functions of the system.It has also been vigorously promoted by companies including ARM and Xilinx.This article designs a configurable interface that connects the FeRAM and AHB buses.It supports the connection of various types of FeRAM chips.By adjusting the internal function configuration registers,various different timing requirements of FeRAM can be realized.Based on the UVM verification methodology,a verification platform was built,and different side use cases were tested while achieving coverage collection.The interface design part mainly introduces the research background and research significance of AHB bus and FeRAM memory,and also explained the significance of UVM verification methodology and research status at home and abroad.Then explained the foundation of UVM verification methodology,including the history of language System Verilog and the language features.The UVM verification platform includes the structure of the UVM verification platform,the UVM phase mechanism,the UVM objection mechanism,the UVM sequence mechanism,and the UVM communication mechanism.These mechanisms are all important mechanisms related to the establishment and operation of the verification platform.Then it introduces the function of the design of the SOC-oriented FeRAM interface,the configuration of various modes of registers,and the configuration of various time parameters.Subsequently,the design features and functional characteristics of each small module are described in detail.At the end of this chapter is introduced the specific parameter configuration when connecting with a FeRAM chip called FM28V100.The configuration of the function register makes the design fit perfectly with this type of FeRAM.The verification section introduces the entire UVM-based verification platform.The entire platform construction from verification plan to verification,including detailed introduction of some important components such as interface,driver,monitor,etc.The generation and operation of the incentive sequence for the entire platform are explained in detail.After introducing these,it is an introduction to the setting and collection of assertions and functional coverage.The article ends with a description of the simulation results.Register test,data transmission test,and abnormal test are selected as the three typical side use cases as their representatives,and their simulation results and corresponding timing diagrams are shown to verify the design correctness.At the end of the article is an analysis of coverage,as long as it is divided into code coverage,function coverage,and assertion coverage.Analyze the coverage of these coverage rates and make reasonable explanations for the areas that are not covered.